Performance of many electronic devices, such as transistors, solar cells, thermo-electric (TE) devices can be improved if carrier mobility is increased. Prior calculations show that Si and Ge have Type-II band gap alignment in cubically strained and relaxed layers. Quantum wells and super lattices with Si, Ge, and SiGe have been good noble structures to build high electron mobility layers and high hole mobility layers. However, the atomic lattice constant of Ge is bigger than that of Si, and direct epitaxial growth generates a high density of misfit dislocations which decreases carrier mobility and shortens the life time of devices. Known configurations utilize special buffer layers such as super lattice or gradient indexed layers to grow Ge on Si wafers or Si on Ge wafers. The growth of these buffer layers takes extra time and effort. For example, the layers can be subject to a post-annealing process to remove dislocations by dislocation gliding inside of the buffer layer or layers.